A computer system typically includes a video system that displays information for a computer user. In a typical video system, a video controller accesses data stored in video memory and drives a display unit, such as a cathode ray tube, to display the stored information, as understood by one skilled in the art. The video memory typically includes specialized dynamic random access memories ("DRAM"), such as a synchronous graphics DRAM ("SGRAM"), which include special functions that enable the video controller to more efficiently access stored video data and drive the display unit. Such special functions typically include bit-masking, byte-masking, and block write functions. In bit-masking, selected bits of write data applied on a data bus of the SGRAM are masked from corresponding addressed memory cells so the data stored in those cells is not overwritten. Byte-masking is analogous to bit-masking except that bytes of write data applied on the data bus are selectively masked from eight corresponding memory cells. The block write function enables the SGRAM to transfer a single bit of data to a group or block of memory cells, which reduces the time it takes to transfer the same data to a large number of memory cells. A typical application of the block write function is writing data corresponding to a desired background color for a video screen to a plurality of memory cells in the SCRAM.
FIG. 1 is a functional block diagram of a portion of a conventional SGRAM 100 including a conventional block write circuit 102 coupled to a memory-cell array 104 including a plurality of memory cells (not shown) arranged in rows and columns. A block 106 of memory cells in the array 104 is shown, and corresponds to a group of eight memory cells in an activated row in the array. A number of digit lines DL0-DL7 are shown coupled to respective memory cells in the block 106. One skilled in the art will realize the depiction of the array 104 has been simplified for ease of explanation, and that components such as sense amplifiers and complementary signal lines have been omitted for the sake of brevity.
The block write circuit 102 includes a column mask decoder 108 receiving a number of column mask bits CM0-CM7 stored in a column mask register 110. The column mask bits CM0-CM7 correspond to data placed on respective data terminals DQ0-DQ7 coincident with a block write command applied to the SGRAM 100, as understood by one skilled in the art. In response to the column mask bits CM0-CM7, the column mask decoder 108 activates a number of column select signals CSEL0-CSEL7. When one of the column mask bits CM0-CM7 is set, the column mask decoder 108 deactivates the corresponding column select signal CSEL0-CSEL7, and when one of the mask bits CM0-CM7 is cleared, the column mask circuit 108 activates the corresponding column select signal CSEL0-CSEL7. A number of input/output transistors 112a-h are coupled between the digit lines DL0-DL7, respectively, and an input/output or input/output line I/O1. Each of the transistors 112a-h receives on its gate a respective one of the column select signals CSEL0-CSEL7. The transistors 112a-h each turn ON when the applied one of the column select signals CSEL0-CSEL7 is active, and thereby couples the input/output line I/O1 to the corresponding digit lines DL0-DL7. When any of the column select signals CSEL0-CSEL7 is inactive, the corresponding transistors 112a-h turn OFF, isolating the corresponding digit lines DL0-DL7 from the input/output line I/O1.
A write driver 114 receives on its input either a color bit CR0 or a write data bit applied on the data terminal DQ0, and applies the data on its input to the input/output line I/O1 in response to a mask signal M received on an enable input. An AND gate 116 develops the mask signal M in response to a byte-mask signal DQM0 applied on a first input and a mask bit MR0 applied on a second input. When the mask bit MR0 is set low or the byte-mask signal is active high, the AND gate 116 drives the mask signal M active low, and when the mask bit MR0 is cleared high and the byte-mask signal DQM0 is inactive low, the AND gate 116 drives the mask signal M inactive high. In operation during a standard write operation, conventional address decode circuitry (not shown in FIG. 1) decodes address signals applied to the SGRAM 100 and activates a corresponding memory cell in the array 104, as understood by one skilled in the art. The write driver 114 then transfers data applied on the terminal DQ0 onto the input/output line I/O1 when the mask signal M is inactive high, and places its output in a high-impedance state to isolate or "mask" this data from the input/output line I/O1 when the mask signal M is active low.
In operation during a block write data transfer, the block write circuit 102 transfers the color bit CR0 to selected ones of the memory cells in the block 106, as will now be described in more detail. During a block write, the address decode circuitry once again decodes address signals applied to the SGRAM 100, and activates corresponding memory cells in the array 104, as understood by one skilled in the art. If either the mask bit MR0 is set or the byte-mask signal DQM0 is active high, the write driver 114 places its output in a high impedance state, masking the color bit CR0 from the memory cells in the block 106 independent of the state of the column select signals CSEL0-CSEL7. In this situation, the data stored in the block 106 is not altered during the block write operation. When the mask bit MR0 is cleared and the byte-mask signal DQM0 is inactive low, the write driver 114 places the color bit CR0 on the input/output line I/O1, and the column mask decoder 108 activates selected ones of the column select signals CSEL0-CSEL7 in response to the column mask bits CM0-CM7. In response to the column select signals CSEL0-CSEL7, selected ones of the transistors 112a-h turn ON, coupling the corresponding digit lines DL0-DL7 to the input/output line I/O1. The color bit CR0 is then transferred through the activated ones of the transistors 112a-h and over the corresponding digit lines DL0-DL7 to respective memory cells in the block 106. If any of the column mask bits CM0-CM7 is set, the corresponding one of the column select signals CSEL0-CSEL7 is deactivated, turning off the associated one of the transistors 112a-h and thereby masking the color bit CR0 from the corresponding memory cell in the block 106. For example, when the column mask bit CR6 is set, the column select signal CSEL6 is deactivated, turning OFF the transistor 112g and thereby masking the color bit CR0 from the memory cell in the block 106 coupled to the digit line DL6. In this way, the column mask decoder 108 masks the color bit CR0 from respective cells within the block 18, which is known as "column masking."
From this description, it is seen that during a block write, several of the transistors 112a-h are typically simultaneously activated, coupling several of the digit lines DL0-DL7 to the input/output line I/O1. In fact, when none of the column mask bits CM0-CM7 is set, all of the transistors 112a-h are turned ON, coupling all of the digit lines DL0-DL7 to the input/output line I/O1. As more digit lines DL0-DL7 are coupled to the input/output line I/O1, the load presented by the input/output line I/O1 increases, and this increased load must be driven by the write driver 114. The load presented by the input/output line I/O1 increases because each of the digit lines DL0-DL7 coupled to the input/output line I/O1 presents an additional parallel load the write driver 114 must drive. The additional load presented by each of the digit lines DL0-DL7 includes the load presented by a sense amplifier (not shown in FIG. 1) coupled to the digit line, along with the additional capacitance presented by the digit line, as understood by one skilled in the art. As a result of the additional load presented by the input/output line I/O1, it takes longer for the write driver 114 to drive the voltage on the input/output line I/O1 to the desired level, and thereby increases the time it takes the conventional block write circuit 102 to perform each block write data transfer. One skilled in the art will appreciate that during standard write data transfers, a single digit line DL is coupled to the input/output line I/O1, reducing the load driven by the write driver 114 relative to block write transfers, and thereby reducing the time required to perform such standard write transfers.
Although the conventional block write circuit 102 typically increases the time required for performing block write operations, the circuit performs satisfactorily in most conventional SGRAMs. As the speed of microprocessors and bandwidths of memory devices steadily increase, however, the time for performing block write operations becomes more critical. In addition, the column masking performed by the conventional block write circuit 102 may be difficult to implement in many new memory devices, such as packetized DRAMs and Embedded DRAMs, having very wide internal data paths. The internal data path includes the input/output lines I/O, and a wide internal data path accordingly includes more such lines. With a wide internal data path, the number of input/output lines I/O associated with each array increases and the number of column select signals CSEL associated with each array typically decreases. The number of column select lines decreases because for each column select signal CSEL more data is transferred out of the array on the input/output lines I/O. For example, in an array where each row includes 128 columns and 64 input/output lines (i e., a 64-bit internal data bus) are associated with the array, only two column select lines CSEL are required, one to transfer the data stored in the memory cells in the first 64 columns onto the respective input/output lines, and a second column select signal to do the same for the data stored in the second 64 columns. As the number of column select signals CSEL decreases, the approach illustrated in FIG. 2 for performing column masking during block write operations may be difficult to implement since the column mask decoder 108 no longer applies separate column select signals CSEL to each column select transistor. For example, in the array described above having 128 columns of memory cells and 64 associated input/output lines, the column select transistors associated with the first 64 columns have their gates coupled together to receive the first column select signal. In this situation, individual column select transistors cannot be separately activated since their respective gates are coupled together.
There is a need for a block write circuit in a memory device having a wide internal data path that decreases the time required for performing block write operations and performs column masking of bits within each block.